1. Field of the Invention
The present invention relates to integrated circuit (IC) technology, and in particular, relates to an electrical-programmable antifuse element for integrated circuit (IC) devices.
2. Description of the Related Art
Integrated circuit (IC) devices are usually made with all internal connections set during the manufacturing process. However, due to high development costs, long manufacturing times, and high manufacturing tooling costs for forming such integrated circuits, users often desire circuits which can be configured or programmed in the field. Such circuits are called programmable circuits and they usually contain programmable links. Programmable links are electrical interconnects which are either broken or created at selected electronic nodes by the user after the integrated circuit device has been fabricated and packaged in order to activate or deactivate respective selected electronic nodes.
One type of the programmable links is a fuse element. The programmable links in the IC devices are programmed by blowing the fuse element at selected cross-over points to create an open circuit. The combination of blown and unblown links represents a digital bit pattern of ones and zeros signifying data which the user wishes to store in the IC device.
In addition, another type of programmable link is an antifuse element and has been developed for integrated-circuit devices. Instead of the programming mechanism causing an open circuit in the case with fuse elements, the programming mechanism in the antifuse element creates a short circuit or a relatively low resistance link therein.
As shown in FIG. 1, U.S. Pat. No. 5,163,180 discloses a conventional antifuse 10 with a structure as a conventional transistor. The antifuse 10 comprises a silicon substrate 12 of a first conductivity type, a gate dielectric layer 14 formed over the silicon substrate 12, a gate 16 formed on the gate dielectric layer 14, first and second regions 18 and 20 of a second conductivity type, spacers 22 and 24 formed at the edges of the gate 16, third and fourth regions 26 and 28 of the second conductivity type, an insulating region 30 formed over the silicon substrate 12, contacts 32 and 34 formed in the insulating region 30 to regions 26 and 28, and a contact 36 formed in the insulating region 30 formed to the gate 16.
Before programming, the antifuse 10 is an open circuit, wherein a resistance between the gate 16 and the regions 18, 20, 26, and 28 in the silicon substrate 12 is higher than 1×109 ohms. A low resistance filament 38 may be formed between the regions 20 and/or 28 and the gate 16 by applying a programming voltage in the range of 8-16 volts on the region 28 with respect to the substrate, with the region 26 held at the substrate potential while the gate 16 is grounded or biased at a slightly positive voltage, i.e., a voltage in the approximate range of 0-2 volts, with respect to the substrate.
The antifuse 10 shown in FIG. 1 can be programmed by a grounding region 26, a holding gate electrode 16 at a low voltage such as 2 volts, and placing a high voltage of approximately 12 volts on the region 28. All voltages are measured with respect to the substrate 12. Under these conditions, the device will be brought into a snap-back breakdown. Snap-back breakdown is a well known phenomenon, characterized in the structure of FIG. 1 by turning on of the parasitic NPN bipolar transistor having regions 18 and 26 as its emitter, substrate 12 as its base, and regions 20 and 28 as its collector. Snap-back breakdown is further characterized by a rise in the current flowing into regions 20 and 28 and by a high-electric-field existing at or near the junction between the regions 20 and 28 and the substrate 12. The combination of high current density and high electric field results in the generation of holes through avalanche-impact ionization and subsequent acceleration of these holes. Some of the energetic holes (or hot holes as they are commonly called) are injected into the dielectric 14. It is known that hole injection into a dielectric such as SiO2 causes or accelerates the dielectric breakdown process.
Under the snap-back breakdown condition, the dielectric 14 in the antifuse of FIG. 1 can be broken down in milliseconds or a shorter time. After breakdown, the contact 36 will be electrically connected to the contact 34 through gate 16, with an ohmic connection through the rupture in the dielectric 14 located over regions 20 and/or 28. Thus, the antifuse 10 is programmed.
However, the antifuse 10 disclosed in U.S. Pat. No. 5,163,180 has a complex structure and occupies a great footprint over the substrate 12. In addition, a high current density and a high electric field are needed to program the antifuse 10. The above drawbacks are not desired while sizes and device densities of an integrated circuit are further decreased.